CMOS (Complementary Metal Oxide Semiconductor) image sensors have become the dominant solid state imaging technology due to their lower cost, superior performance, and higher resolution than CCD (charge coupled device) imager. In addition, signal processing logic can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand alone imaging device. The most popular active pixel sensor structure consists of three or four transistors and an N+/P− well photodiode, but has the drawback of a relatively large dark current. The dark current decreases signal-to-noise ratios for the image sensor and decreases image quality. Another active pixel sensor design is pinned photodiode (PPD) which would be called “buried photodiode” since it has PNP (or NPN) junction structure which is buried in a substrate near the silicon surface. The pinned photodiode structure can increase the depletion depth to bring about high quantum efficiency in converting incident photons into electric charges, and has gained favor for its ability to have good color response for blue light, as well as advantages in dark current density.
The pinned photodiode structure, however, is not compatible with shallow trench isolation (STI) technology because it is difficult to control shallow junction at the STI sidewall. The trenches used for trench isolation are generally dry etched and, as a result, the trench surfaces usually have a large number of interface states, which lead to high surface generation velocity and a large dark current. The trench forming processes also cause crystalline defects (such as dislocations and stacking faults), which reduce carrier generation lifetime and increase dark current. The sidewalls and bottom portion of the STI structure have a higher silicon density than the substrate, creating a higher density of trap sites that are areas in the silicon dioxide/silicon interface and trap electrons or holes. In a conventional trench-isolated photodiode, a buffer of P-well region is provided between the STI structure and the diffusion region that forms the PN junction of the photodiode. This design only lowers trap sites at the interface near the silicon surface, but fails in solving the high-density trap sites at the STI sidewall. Accordingly, it is desirable to provide a pinned photodiode with STI technique for reducing dark current caused by higher trap sites along the STI sidewall.